Question

In the following digital circuit, the delay of both the NAND gates is 4 nanoseconds (ns) and the delay of the NOT gate is 1 ns. If a 10 MHz clock signal with 50% duty cycle is given as the input, the duty cycle of the output is %.
(Answer in integer)

Hint:

The circuit is a cross coupled NAND pair driven by Input and its delayed inverse, so it settles to Output = NOT(Input), but the rising and falling edges of Output take different total delays (4 ns vs 9 ns) because a NAND gate with one input forced to 0 does not need to wait on its other input.

Answer 1

Correct Answer: 55

Step 1: Understanding the Concept:
The Input and its delayed inverse drive the two inputs of a cross coupled NAND pair, so the loop behaves as an inverter for the Output once it settles: Output $= \overline{\text{Input}}$.
But the two edges of Output do not arrive after the same delay, because one edge only needs one gate to flip (the 0 forces NAND output to 1 shortcut) while the other edge must ripple through the NOT gate and both NAND gates.

Step 2: Key Formula or Approach:
Let $t_r$ be the delay from an Input falling edge to the resulting Output rising edge, and $t_f$ be the delay from an Input rising edge to the resulting Output falling edge.
If Input has period $T$ and stays high for time $T_H$ and low for $T_L$ (here $T_H=T_L=T/2$ since duty is 50%), Output's high time is simply shifted by the gap between the two delays:
\[ \text{Output high time} = T_L + (t_f - t_r) \]
This holds because Output goes high $t_r$ after Input falls, and goes low $t_f$ after Input next rises, so the high window gains exactly $(t_f-t_r)$ compared with Input's own low window.

Step 3: Detailed Explanation:
Find $t_r$: when Input falls, the top NAND immediately has one input at $0$, and a NAND gate with any input at $0$ outputs $1$ right after its own propagation delay. So $t_r = 4$ ns (one NAND delay only).
Find $t_f$: when Input rises, the top NAND cannot resolve on its own since neither of its inputs is forced yet; the change must go through the NOT gate ($1$ ns), then the bottom NAND ($4$ ns), then the top NAND ($4$ ns). So $t_f = 1+4+4 = 9$ ns.
Clock: frequency $10$ MHz gives period $T = 1/(10\times 10^6) = 100$ ns, and 50% duty gives $T_H=T_L=50$ ns.
Apply the formula:
\[ \text{Output high time} = T_L + (t_f - t_r) = 50 + (9-4) = 55 \text{ ns} \]
Check with the low time: Output low time $= T_H - (t_f-t_r) = 50-5=45$ ns, and $55+45=100$ ns $=T$, confirming the split is correct.

Step 4: Final Answer:
Duty cycle of Output $= \dfrac{55}{100}\times100 = 55\%$.
\[ \boxed{55\%} \]