Which of the following functions represent(s) the output of the CMOS logic-gate shown in the circuit below?
Show Hint
Trace the NMOS pull-down network: A alone in parallel with (B in series with C), so \(f=\overline{A+BC}\); check the PMOS side too, since the two halves of this circuit do not form a valid complementary pair.
Step 1: Build a truth table for the network exactly as drawn, instead of simplifying symbolically first.
Define "PU on" as the condition under which the pull-up (PMOS) side conducts, and "PD on" as the condition under which the pull-down (NMOS) side conducts, using the transistor placement read off the figure: $\text{PU on} = \overline{C}\cdot(\overline{A}+\overline{B})$ (top PMOS gated by $C$ in series with a parallel pair gated by $A,B$), and $\text{PD on} = A + B\cdot C$ ($A$-gated NMOS alone in parallel with a series pair gated by $B,C$). Step 2: Evaluate both expressions for every combination of A, B, C.
Going through all $8$ cases:
$(0,0,0)$: PU $=1$, PD $=0$, output driven high, consistent.
$(0,0,1)$: PU $=0$, PD $=0$, neither side conducts, output floats.
$(0,1,0)$: PU $=1$, PD $=0$, consistent, output high.
$(0,1,1)$: PU $=0$, PD $=1$, consistent, output low.
$(1,0,0)$: PU $=1$, PD $=1$, both sides conduct at once, a direct short from $V_{DD}$ to ground.
$(1,0,1)$: PU $=0$, PD $=1$, consistent, output low.
$(1,1,0)$: PU $=0$, PD $=1$, consistent, output low.
$(1,1,1)$: PU $=0$, PD $=1$, consistent, output low. Step 3: Interpret the two failing rows.
Six of the eight rows behave like a normal logic gate, with exactly one of PU/PD conducting. But at $(A,B,C)=(0,0,1)$ the output is left floating (undefined, since neither rail drives it), and at $(A,B,C)=(1,0,0)$ both rails try to drive the output at once (a short circuit). A genuine logic gate must have exactly one of PU, PD active for every input combination; this circuit fails that requirement for two of the eight rows. This is a hard contradiction baked into the artwork, not a matter of interpretation. Step 4: Extract the "intended" function from the unambiguous half of the circuit.
The pull-down network alone is a completely standard structure (one lone transistor in parallel with a two-transistor series stack) and it unambiguously computes $f=\overline{A+BC}$ once complemented. Expanding by De Morgan,
\[
f=\overline{A}\cdot\overline{B\,C}=\overline{A}(\overline{B}+\overline{C})
\]
which is exactly options (B) and (C), shown to be algebraically identical by expanding either one. Step 5: Explain why (A) and (D) are the wrong pair.
Expanding option (D), $\overline{A(B+C)}=\overline{A}+\overline{B\,C}=\overline{A}+\overline{B}\,\overline{C}$, which is exactly option (A). So (A) and (D) form their own matching pair, algebraically equal to each other, but structurally different from what the pull-down network computes (it swaps which variable, $A$ or $B/C$, sits inside the OR versus outside it). Since the unambiguous half of the circuit (the pull-down network) points squarely at options (B) and (C), these are the best-supported choice, even though the circuit's other half (the pull-up network) does not agree with it and produces neither pair cleanly, which is the root cause of the flaw.
Because the two halves of the drawn circuit do not form a valid complementary pair, and produce a floating output for one input pattern and a short circuit for another, this question was withdrawn by GATE and full marks were given to every candidate (MTA), rather than there being one clean, defensible option.
\[
\boxed{f=\overline{A+BC}=\overline{A}(\overline{B}+\overline{C})\ \text{(best supported: options B and C)}}
\]
