In the phase-locked-loop (PLL) circuit shown below, the output of the VCO (voltage-controlled oscillator) is a digital square wave.
If the input is a square wave at \(10\) kHz, the steady state frequency of the output is kHz (rounded off to the nearest integer).
Show Hint
In lock, the two signals reaching the phase detector must have the same frequency. Divide the input by \(20\) and the output by \(1024\), then set those two equal and solve for the output frequency.
Step 1: Picture the loop as two frequency dividers feeding a comparator.
All the phase detector needs is two pulse trains at the same rate. The input branch produces one pulse for every $20$ cycles of the $10$ kHz input signal. The feedback branch produces one pulse for every $1024$ cycles of the VCO output.
Step 2: Work out the rate on the input branch.
\[ r_{in} = \frac{10 \text{ kHz}}{20} = 0.5 \text{ kHz} \]
For the loop to stay locked, the feedback branch must produce pulses at this same rate, $r_{in} = 0.5$ kHz.
Step 3: Work backwards through the feedback divider.
The feedback divider takes the VCO frequency $f_{out}$ and divides it by $1024$ to give $0.5$ kHz, so
\[ f_{out} = 0.5 \times 1024 = 512 \text{ kHz} \]
Final Answer:
The VCO settles at $512$ kHz once the loop locks.
\[ \boxed{f_{out} = 512 \text{ kHz}} \]
