A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB. TLB
reach is defined as the total amount of physical memory that can be accessed
through the TLB entries. The paging system uses pages of size 4 KB. The virtual
address space is 64 GB and physical address space is 1 GB. If each TLB entry stores
a 4-bit process id, page number, frame number, and a 2-bit control field, then the
size of the TLB (in bytes) is ___________. (answer in integer)
Note: \(1\mathrm{K}=2^{10}\), \(1\mathrm{M}=2^{20}\), \(1\mathrm{G}=2^{30}\)
This question can be solved by breaking the TLB into 'how many entries' and 'how big is each entry,' then multiplying the two.
Finding the entry count: The TLB reach tells us how much physical memory the TLB can cover in one shot. Since reach = entries \(\times\) page size, we get:
\[entries = \frac{1\,MB}{4\,KB} = \frac{2^{20}}{2^{12}} = 2^8 = 256 \text{ entries}\]Finding the width of each field in an entry:
Adding up one entry's width:
\[4 + 24 + 18 + 2 = 48 \text{ bits} = 6 \text{ bytes per entry}\]Scaling up to the whole TLB: multiply the per-entry size by the number of entries computed from the reach:
\[256 \times 6 \text{ bytes} = 1536 \text{ bytes}\]So the TLB occupies a total of \(1536\) bytes.
Consider a three-level page table to translate a 39-bit virtual address to a physical address as shown. The page size is 4KB and page table entry size at every level is 8 bytes. A process \( P \) is currently using 2GB virtual memory mapped to 2GB physical memory. The minimum amount of memory required for the page table of \( P \) across all levels is \(\underline{\hspace{2cm}}\) KB. 