Step 1: Break down the 16 bit instruction word.
Each instruction carries one opcode plus up to three operands, and the whole word is 16 bits. If the opcode width is $p$ bits and each operand width is $q$ bits, then $p+3q=16$ whenever all three operand slots are used. We are told directly that $p=7$ (opcode is 7 bits) and $q=3$ (each operand, hence each register field, is 3 bits). Check: $7+3(3)=7+9=16$, so the numbers are self consistent.
Step 2: Count opcodes from the opcode width.
A 7 bit field has $2^7=128$ possible patterns, so the processor supports at most 128 distinct opcodes. Statement (B) matches this, and statement (D), which claims 512 (that needs $2^9$), does not.
Step 3: Count registers from the operand width.
A 3 bit register field has $2^3=8$ possible patterns, so at most 8 internal registers can be addressed. Statement (C) matches this exactly, and statement (A), which claims 16 registers (that would need a 4 bit field), does not.
Step 4: Combine the two results.
The opcode count and the register count come from two separate, independent fields in the instruction word. The register field size fixes the register count and the opcode field size fixes the opcode count, so both (B) and (C) hold at the same time.
\[ \boxed{\text{Options (B) and (C) are correct}} \]