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List of top Electronics Engineering Questions on Digital Electronics and Logic Gates
The following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1 V. Ignoring the body-effect, the output voltages at P, Q and R are,
CUET (PG) - 2025
CUET (PG)
Electronics Engineering
Digital Electronics and Logic Gates
An 8-bit ADC converts analog voltage in the range of 0 to +5 V to the corresponding digital code as per the conversion characteristics shown in the figure. For \(V_{in}\) = 1.9922 volt, which of the following digital output, given in hex, is true?
CUET (PG) - 2025
CUET (PG)
Electronics Engineering
Digital Electronics and Logic Gates
Neglecting the delays due to the logic gates in the circuit shown in the figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with the clock, is
CUET (PG) - 2025
CUET (PG)
Electronics Engineering
Digital Electronics and Logic Gates
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter.
CUET (PG) - 2025
CUET (PG)
Electronics Engineering
Digital Electronics and Logic Gates
The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns, is
CUET (PG) - 2025
CUET (PG)
Electronics Engineering
Digital Electronics and Logic Gates
The Boolean function f implemented in the figure using two input multiplexers is
CUET (PG) - 2025
CUET (PG)
Electronics Engineering
Digital Electronics and Logic Gates