The following circuit employing pass transistor logic, all NMOS transistors are identical with a threshold voltage of 1 V. Ignoring the body-effect, the output voltages at P, Q and R are,
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For an NMOS pass transistor with its gate tied to VDD, the maximum output high voltage (\(V_{OH}\)) is \(VDD - V_{th}\). In a chain, this drop only occurs at the first stage if the body effect is ignored. Subsequent stages will pass this already-dropped voltage without further degradation.
Step 1: First transistor analysis (output at P).
This NMOS pass transistor passes a strong '0' but a weak '1'. Its maximum output voltage is limited by the gate and threshold voltages.
With a 5V drain input and 5V gate voltage, the output at the source (Vp) is determined by when the transistor stops conducting, i.e., when \(V_{GS} = V_{th}\).
\[ V_G - V_S = V_{th} \]
\[ 5V - V_p = 1V \implies V_p = 4V \]
Therefore, the output voltage at P is 4V.
Step 2: Second transistor analysis (output at Q).
This transistor receives \(V_p = 4V\) at its drain and has a 5V gate voltage. The output is Vq.
The maximum possible output is \(V_G - V_{th} = 5V - 1V = 4V\).
Since the drain input is 4V, the source voltage cannot exceed 4V. The transistor conducts as long as \(V_{GS}>V_{th}\) (i.e., \(5V - V_q>1V\)) and \(V_{DS}>0\). As Vq approaches 4V, \(V_{DS} = V_p - V_q\) approaches 0, stopping current flow. Thus, Vq settles at 4V.
Step 3: Third transistor analysis (output at R).
The logic mirrors Step 2. With \(V_q = 4V\) at the drain and a 5V gate, the maximum possible output is \(V_G - V_{th} = 4V\). Consequently, the output Vr will also be 4V.
Given the instruction to ignore the body effect, the threshold voltage remains constant at 1V for all transistors, preventing voltage degradation beyond the first stage. The outputs are (4V, 4V, 4V).
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