List of top Electrical Engineering Questions on Digital Logic

Mealy output depends on:

A Decoder with n inputs has the following number of outputs:

A full adder can be built using:

The Karnaugh map is used for:

The MSB frequency of a 4-bit ripple counter with 16 MHz clock is

Minimum number of 2-input NAND gates required for implementing the logic \( F = AB + A'C \) is:

A first-order high-pass RC filter has cutoff frequency \(\text{f}_\text{c}=1\text{ kHz}\). If the magnitude of the transfer function is measured at \(\text{f}=500\text{ Hz}\), the gain magnitude is

A synchronous 3-bit binary counter is currently in state \(\text{Q}_2\text{Q}_1\text{Q}_0=101\). After two clock pulses, its state will be