List of top Data Science A.I Cyber Security and Computer Sci. Questions on Microprocessors and Interfacing

Match List - I with List - II.

List - I		List - II
A.	Machine cycle	I.	Time required to complete one operation (Fetch/read/write)
B.	T-state	II.	One subdivision of a machine cycle
C.	Instruction cycle	III.	Time required to complete one instruction
D.	Opcode fetch	IV.	Machine cycle to get instruction opcode from memory

Choose the correct answer from the options given below:

Consider the following statements :
A. MOV A, M copies data from memory (pointed by HL) to accumulator

B. LXI H, 2025H loads 2025H into register pair HL

C. STA 2050H stores the accumulator content into memory at address 2050H

D. LDA 2050H loads HL with the contents of memory location at 2050H

Choose the correct answer from the options given below :

Consider the flags in flag Register from left to right :
A. S

B. Z

C. AC

D. P

E. CY

Choose the correct answer from the options given below :

Given below are two statements :
one is labelled as
Assertion (A) and the other is labelled as
Reason (R).
Assertion (A) :
During memory interfacing, address decoding is required to select the desired memory chip.
Reason (R) :
Each memory chip has unique address range that must be enabled using chip select signals.
In the light of the above statements, choose the most appropriate answer from the options given below :

After execution of ANI 0FH with accumulator = A9H, which flags are affected ?

After ADI 01H when A = FFH, the accumulator and carry flags are :

In case of DMA, after the completion of the transfer, the processor is required to be notified of the completion. This is done through.

Match List I with List II.

List I	List II
A. Supervisor mode	I. Entered when the processor encounters a software interrupt instruction
B. Abort Mode	II. Entered in response to memory fault
C. Fast Interrupt Mode	III. Entered whenever the processor receives an interrupt signal from a designated fast interrupt source
D. Interrupt Mode	IV. Entered whenever the processor receives an interrupt signal from any other source

Cycle stealing mode of DMA operation involves:

Each instruction in an assembly language program has the following fields. What is the correct sequence of these fields?,
(A) Label field
(B) Mnemonic field
(C) Operand field
(D) Comment field
Choose the correct answer from the options given below:

Which of the following in 8085 microprocessor performs HL = HL + HL?

The contents of register BL and register AL of 8085 microprocessor are 49H and 3AH, respectively. The contents of AL, the status of carry flag (CF), and sign flag (SF) after executing the instruction SUB AL, BL are:

Choose the software interrupt from the following list:

The number of wait states required to interface 8279 to 8086 with an 8MHz clock are: