The number of wait states required to interface 8279 to 8086 with an 8MHz clock are:

Question

In case of DMA, after the completion of the transfer, the processor is required to be notified of the completion. This is done through.

Answer 1

The 8279 programmable keyboard/display interface operates at a slower clock cycle than the 8086 microprocessor (8 MHz). To synchronize data transfer between these devices, wait states are introduced. For an 8 MHz clock, calculations show that 3 wait states are required for proper interfacing.

List I	List II
A. Supervisor mode	I. Entered when the processor encounters a software interrupt instruction
B. Abort Mode	II. Entered in response to memory fault
C. Fast Interrupt Mode	III. Entered whenever the processor receives an interrupt signal from a designated fast interrupt source
D. Interrupt Mode	IV. Entered whenever the processor receives an interrupt signal from any other source

Firm 2	Cooperate	Compete
Firm 1	5, 5	0, 10
Compete	10,0	2, 2

The number of wait states required to interface 8279 to 8086 with an 8MHz clock are:

Show Hint

The Correct Option is B

Solution and Explanation

Top Questions on Microprocessors and Interfacing

Questions Asked in CUET (PG) exam