List of top Computer Organization and Architecture Questions on Instruction Pipelining

A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is \(\underline{\hspace{1cm}}\).
Consider a pipelined processor with 5 stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage except EX takes one cycle. The EX stage takes one cycle for ADD and two cycles for MUL. Given the instruction sequence:
\[ \text{ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL} \] The speedup (rounded to 2 decimal places) is \(\underline{\hspace{2cm}}\).
A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds.
The register delay between stages is 5 nanoseconds. The total time to execute 100 independent instructions is \(\underline{\hspace{2cm}}\) nanoseconds.