To compute the speedup of the pipelined processor, we must first understand the cycle requirements for executing the instruction sequence both in pipelined and non-pipelined processors.
The instruction sequence given is: ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL.
Non-Pipelined Execution:
In a non-pipelined processor, each instruction completes all stages before the next begins.
- ADD takes: \(5\) cycles (one per stage)
- MUL takes: \(6\) cycles (one for IF, ID, MEM, WB, and two for EX)
Total cycles for sequence: \[(5+6)\times4=44\text{ cycles}\]
Pipelined Execution:
1. In a pipelined processor, multiple instructions overlap.
2. ADD requires \(1\) cycle per stage and \(1\) for EX, so first ADD completes at cycle \(5\).
3. MUL requires \(2\) EX cycles, finishing at cycle \(7\) assuming perfect pipeline.
4. Subsequent ADD starts 1 cycle after previous completes, finishing in \(5\) cycles.
5. Likewise, subsequent MUL starts and finishes 7 cycles later.
Let’s calculate the cycles:
- First ADD completes at cycle: \(5\)
- First MUL completes at cycle: \(8\) (2 additional for overlap)
- Second ADD completes at cycle: \(10\)
- Second MUL completes at cycle: \(13\)
- Third ADD completes at cycle: \(15\)
- Third MUL completes at cycle: \(18\)
- Fourth ADD completes at cycle: \(20\)
- Fourth MUL completes at cycle: \(23\)
Total cycles for pipelined execution: \(23\)
Speedup Calculation:
Speedup is given by the ratio of non-pipelined to pipelined cycles: \[\text{Speedup}=\frac{44}{23}\approx1.91\]
Validation:
The calculated speedup \(1.91\) is within the expected range \(1.87,1.87\). Thus, our calculations are correct.