Step 1: Ask which FPGA resource a synthesis tool maps ordinary gates and flip-flops onto. That resource is the Configurable Logic Block.
Step 2: A CLB pairs a look-up table, which can reproduce any truth table for combinational logic, with a register that holds a value across clock edges for sequential logic.
Step 3: The remaining options are specialised helpers: DSP slices accelerate arithmetic, the PLL manages clocks, and Block RAM provides on-chip memory. They support a design but do not form the core logic fabric.
Step 4: Therefore the general-purpose logic element is the CLB.
\[\boxed{\text{Configurable Logic Blocks}}\]