Step 1: Compare how the two families switch their transistors.
TTL circuits are built from bipolar junction transistors, and in the process of switching states these transistors typically pass through an active region where both the top and bottom halves of an output stage can conduct simultaneously for a brief moment, drawing a noticeable current straight from supply to ground even while idle in some configurations.
Step 2: Look at what CMOS does differently.
CMOS gates are built from a complementary pair of MOSFETs, one PMOS and one NMOS, stacked so that for any steady logic input exactly one of the pair is conducting and the other is fully off. Because there is never a direct low resistance path from supply to ground in steady state, essentially no current flows except for a brief pulse during switching and a very small leakage current.
Step 3: Translate this into practical power figures.
This difference means a CMOS chip sitting idle, or switching only occasionally, consumes power that can be orders of magnitude lower than an equivalent TTL circuit doing the same job, which is why CMOS dominates in battery powered and densely packed digital systems.
\[ \boxed{\text{Much reduced power dissipation}} \]