Step 1: Write the NAND function algebraically.
With positive logic, a two input NAND gate produces the output $Y = \overline{AB}$, meaning the output is low only when both inputs are simultaneously high, and high in every other case.
Step 2: Expand this using De Morgan's theorem.
De Morgan's theorem lets us rewrite the complement of a product as a sum of complements, so $\overline{AB} = \overline{A} + \overline{B}$. This tells us that, on paper, the NAND function is logically identical to an OR gate whose two inputs have first been individually inverted.
Step 3: Connect the inverted inputs to negative logic.
Interpreting a signal in negative logic means that a physically low voltage is read as logic 1 and a physically high voltage is read as logic 0, which is exactly equivalent to complementing the input before it reaches an ordinary positive logic gate. Since $\overline{A}$ and $\overline{B}$ are precisely the complemented versions of the original inputs, feeding the same physical NAND gate's inputs but reading them in negative logic reproduces the OR relationship $\overline{A}+\overline{B}$.
Step 4: State the equivalence.
So a NAND gate wired and read with positive logic behaves, functionally, exactly like an OR gate whose inputs are read using negative logic.
\[ \boxed{\text{OR with negative logic input}} \]