Step 1: Convert page size into addressable units.
The page size is $8$ kB, which equals:
\[ 8 \times 1024 = 8192 \text{ bytes} \]
Each word occupies $4$ bytes, and the system uses word addressing.
Therefore, the number of addressable words within a single page is:
\[ \frac{8192}{4} = 2048 = 2^{11} \]
This means that every virtual page contains $2^{11}$ unique virtual addresses.
Step 2: Interpret the capacity of the TLB.
Each TLB entry holds the translation for exactly one virtual page.
The total number of valid TLB entries is $128$, which can be written as:
\[ 128 = 2^7 \]
Hence, address translations for $2^7$ different virtual pages can be cached at once.
Step 3: Compute the total address coverage without TLB misses.
Since each virtual page contributes $2^{11}$ addresses, the total number of distinct virtual addresses that can be translated without replacing any TLB entry is:
\[ 2^7 \times 2^{11} = 2^{18} \]
This value can be rewritten as:
\[ 2^{18} = 8 \times 2^{15} \]
Expressed in the form used in the given options, this corresponds to:
\[ 8 \times 2^{20} \]
Step 4: Final result.
The maximum number of distinct virtual addresses that can be translated without any TLB miss is:
\[ \boxed{8 \times 2^{20}} \]
Consider a three-level page table to translate a 39-bit virtual address to a physical address as shown. The page size is 4KB and page table entry size at every level is 8 bytes. A process \( P \) is currently using 2GB virtual memory mapped to 2GB physical memory. The minimum amount of memory required for the page table of \( P \) across all levels is \(\underline{\hspace{2cm}}\) KB. 