A JK flip-flop has inputs $J = 1$ and $K = 1$.
The clock input is applied as shown. Find the output clock cycles per second (output frequency).

Step 1: Review the JK Flip-Flop Truth Table
For a JK flip-flop, the next state depends on inputs J and K as follows: \[ \begin{array}{c|c|c} J & K & \text{Next State} \\ \hline 0 & 0 & \text{No change} \\ 0 & 1 & 0 \\ 1 & 0 & 1 \\ 1 & 1 & \text{Toggle} \end{array} \]
Here, \( J = 1 \) and \( K = 1 \). Therefore, the flip-flop operates in toggle mode.
Step 2: Analyze the Toggle Operation
In toggle mode, the output switches state at every clock pulse. If the initial output is 0, the sequence becomes: \[ 0 \rightarrow 1 \rightarrow 0 \rightarrow 1 \rightarrow \dots \] A complete output cycle (0 → 1 → 0) requires two clock pulses.
Step 3: Compute the Output Frequency
Since the output changes state on every clock edge but completes one full cycle in two clock pulses: \[ f_{out} = \frac{f_{clk}}{2} \]
Final Result:
\[ \boxed{ f_{out} = \frac{f_{clk}}{2} } \]
Hence, a JK flip-flop with \( J = K = 1 \) functions as a divide-by-2 frequency divider.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).

A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).