In a 4-bit ripple counter, if the period of the waveform at the last flip-flop is 64 microseconds, then the frequency of the ripple counter in kHz is ______________. {(Answer in integer)}
Therefore, the duration of a single clock pulse is:
\(\dfrac{64\,\mu s}{16} = 4\,\mu s\)
This means the clock produces one pulse every \(4\,\mu s\). Converting this interval into a rate:
\(\dfrac{1}{4 \times 10^{-6}} = 2.5 \times 10^5\,\text{Hz}\)
Hence, the input clock frequency is \(\boxed{250\,\text{kHz}}\).
A JK flip-flop has inputs $J = 1$ and $K = 1$.
The clock input is applied as shown. Find the output clock cycles per second (output frequency).

In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns. The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is (answer in MHz).

A 50 \(\Omega\) lossless transmission line is terminated with a load \( Z_L = (50 - j75) \, \Omega.\) { If the average incident power on the line is 10 mW, then the average power delivered to the load
(in mW, rounded off to one decimal place) is} _________.