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List of top Computer Science & Information Technology Questions on Computer Organization and Architecture
Which addressing mode provides the fastest access?
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
What type of conflicts arise when an instruction depends on the result of a previous instruction, but this result is not yet available?
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
In strobe control method, the strobe pulse is controlled by which unit in the CPU?
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
Choose the most common auxiliary memory device.
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
The symbolic notation used to describe the microoperation transfers among registers is called
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
What is the output of selective complement operation of 1010 and 1100?
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
Which of the following register holds memory operand?
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
What is the correct description of CIL instruction?
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
Choose typical program control instructions.
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
What is the product of \[ 1.11\times2^3 \] and \[ 1.0101\times2^6 ? \]
TS PGECET - 2026
TS PGECET
Computer Science & Information Technology
Computer Organization and Architecture
A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?
GATE CS - 2026
GATE CS
Computer Science & Information Technology
Computer Organization and Architecture
Consider $Z = X - Y$, where $X$, $Y$ and $Z$ are all in sign-magnitude form. $X$ and $Y$ are each represented in $n$ bits. To avoid overflow, the representation of $Z$ would require a minimum of:
GATE CS - 2026
GATE CS
Computer Science & Information Technology
Computer Organization and Architecture