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A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

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For a {fully associative cache}: Index bits are always {0}. Tag bits $=$ Address bits $-$ Offset bits.
Updated On: Feb 16, 2026
  • 24 bits and 0 bits
  • 28 bits and 4 bits
  • 24 bits and 4 bits
  • 28 bits and 0 bits
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The Correct Option is D

Solution and Explanation

Step 1: Note the given cache details. 
The cache capacity is $16$ kB, which is equal to $16 \times 1024 = 2^{14}$ bytes.
Each cache block has a size of $16$ bytes, or $2^4$ bytes.
The main memory uses $32$-bit addresses.

Step 2: Compute the total number of cache blocks.
The number of blocks in the cache is obtained by dividing the cache size by the block size:

\[ \text{Number of cache blocks} = \frac{2^{14}}{2^4} = 2^{10} \]

Step 3: Determine the block offset field.
Because the memory is byte-addressable and each block contains $16$ bytes, the number of offset bits is:

\[ \text{Offset bits} = \log_2 16 = 4 \]

Step 4: Determine the index field.
The cache is fully associative, meaning that any memory block can be stored in any cache line.
As a result, no index bits are required:

\[ \text{Index bits} = 0 \]

Step 5: Calculate the tag field size.
A memory address is divided into three parts:

\[ \text{Tag} + \text{Index} + \text{Offset} = 32 \text{ bits} \]

Substituting the known values:

\[ \text{Tag} = 32 - 0 - 4 = 28 \text{ bits} \]

Step 6: Final result.
The number of bits required for the tag and index fields are:

\[ \boxed{28 \text{ bits and } 0 \text{ bits}} \]

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