The initial contents of the 4-bit serial-in-parallel out right-shift register shown in figure is 0110. After three clock pulse applied, the contents of the shift register will be
\[
\text{}
\]
Understanding the Concept:
A feedback shift register uses an XOR logic gate on specific flip-flop outputs to generate the next serial input data bit (\(D_{in}\)). Let the 4-bit register state be represented as \(Q_3 Q_2 Q_1 Q_0\), where bits shift from left to right on each rising clock edge:
• New \(Q_3 = D_{in}\)
• New \(Q_2 = Q_3\)
• New \(Q_1 = Q_2\)
• New \(Q_0 = Q_1\)
From the schematic, the inputs to the XOR gate are taken from the last two flip-flop outputs, which are \(Q_1\) and \(Q_0\). Therefore, the feedback function determining the serial input is:
\[
D_{in} = Q_1 \oplus Q_0
\]
Step 1: Write down the initial state.
The initial content given is:
\[
Q_3 Q_2 Q_1 Q_0 = 0110
\]
Here, \(Q_3 = 0\), \(Q_2 = 1\), \(Q_1 = 1\), and \(Q_0 = 0\).
Step 2: Trace Clock Pulse 1.
First, evaluate the feedback input bit before the shift occurs:
\[
D_{in} = Q_1 \oplus Q_0 = 1 \oplus 0 = 1
\]
Now, perform the right shift operation by introducing \(D_{in} = 1\) at the most significant position:
\[
Q_3 \leftarrow D_{in} = 1
\]
\[
Q_2 \leftarrow Q_3 = 0
\]
\[
Q_1 \leftarrow Q_2 = 1
\]
\[
Q_0 \leftarrow Q_1 = 1
\]
After Clock Pulse 1, the state of the register is: 1011
Step 3: Trace Clock Pulse 2.
Using the new state \(Q_3 Q_2 Q_1 Q_0 = 1011\), find the next feedback input:
\[
D_{in} = Q_1 \oplus Q_0 = 1 \oplus 1 = 0
\]
Performing the right shift operation:
\[
Q_3 \leftarrow D_{in} = 0
\]
\[
Q_2 \leftarrow Q_3 = 1
\]
\[
Q_1 \leftarrow Q_2 = 0
\]
\[
Q_0 \leftarrow Q_1 = 1
\]
After Clock Pulse 2, the state of the register is: 0101
Step 4: Trace Clock Pulse 3.
Using the state \(Q_3 Q_2 Q_1 Q_0 = 0101\), evaluate the feedback input:
\[
D_{in} = Q_1 \oplus Q_0 = 0 \oplus 1 = 1
\]
Performing the final right shift operation:
\[
Q_3 \leftarrow D_{in} = 1
\]
\[
Q_2 \leftarrow Q_3 = 0
\]
\[
Q_1 \leftarrow Q_2 = 1
\]
\[
Q_0 \leftarrow Q_1 = 0
\]
After Clock Pulse 3, the final state of the register is: 1010
This completely matches option (C).
