Question

Race Around condition can be avoided in Digital logic circuits using?

• A. Shift Register
• B. Master-Slave JK Flip Flop
• C. Full Adder
• D. AND Gate

Hint:

In a Master-Slave setup, the "Master" is active during the high level of the clock, and the "Slave" transfers the value on the falling edge, ensuring only one change per cycle.

Answer 1

The Correct Option is B

Step 1: Understanding the Concept:
The race-around condition occurs in a JK flip-flop when $J=1$ and $K=1$ and the pulse width of the clock is too large compared to the propagation delay. This causes the output to toggle multiple times during a single clock pulse.
Step 2: Detailed Explanation:
To prevent the output from toggling more than once per clock pulse:
1. We can use edge-triggering (the flip-flop only changes state at the transition of the clock).
2. We can use a Master-Slave JK Flip-flop. In this arrangement, the master accepts data while the clock is high, but the slave (which controls the output) only changes when the clock goes low. This ensures only one transition per clock period.
Step 3: Final Answer:
The Master-Slave JK Flip Flop is the solution to avoid race-around.