Question

Match List-I with List-II

List-I (Data Bus Status Output)	List-II (Status Signals)
(A) Memory read	(I) 0, 1, 1
(B) Op-code fetch	(II) 0, 1, 0
(C) INTR acknowledge	(III) 0, 0, 1
(D) Memory write	(IV) 1, 1, 1

• A. . (A) = (I), (B) = (II), (C) = (III), (D) = (IV)
• B. (A) = (III), (B) = (IV), (C) = (I), (D) = (II)
• C. (A) = (IV), (B) = (III), (C) = (II), (D) = (I)
• D. (A) = (II), (B) = (I), (C) = (IV), (D) = (III)

Hint:

When dealing with data bus signals, understand that each operation like memory read, write, or op-code fetch corresponds to a unique status signal for the processor.

Answer 1

The Correct Option is A

Step 1: Data Bus Status Signals
The data bus status signals are defined as follows:
- Memory read: (I) 0, 1, 1.
- Op-code fetch: (II) 0, 1, 0.
- INTR acknowledge: (III) 0, 0, 1.
- Memory write: (IV) 1, 1, 1.

Final Answer: \[\boxed{1. \text{(A) = (I), (B) = (II), (C) = (III), (D) = (IV)}}\]