| List I | List II |
|---|---|
| P. Immediate | 1. Element of an array |
| Q. Indirect | 2. Pointer |
| R. Base with index | 3. Element of a record |
| S. Base with offset/displacement | 4. Constant |
Step 1: Instead of starting from the addressing modes, start from the four data elements in List II and ask which addressing mode a compiler would naturally use to reach each one.
Step 2: A constant, item 4, never lives in memory at a variable address, its value is written straight into the instruction stream, so the compiler uses Immediate addressing for it. That fixes P-4.
Step 3: A pointer, item 2, is a variable whose value is itself an address of something else. Reading through a pointer means the CPU first reads the pointer's value and then uses that value as the address of the real operand, exactly the two-hop behavior of Indirect addressing. That fixes Q-2.
Step 4: An array element, item 1, is accessed as base-of-array plus a running index that changes across loop iterations, so the compiler picks a mode built from a base register and a separate index register, i.e. Base with index. That fixes R-1.
Step 5: A record element, item 3, sits at a distance from the start of the record that is fixed once the struct layout is decided at compile time, so the compiler encodes that fixed distance as a displacement added to a base register holding the record's address, i.e. Base with offset/displacement. That fixes S-3.
Step 6: Putting P-4, Q-2, R-1, S-3 together reproduces option (B) again from the reverse direction. Any option that assigns the record element to Q or the pointer to S, such as options (A) and (D), inverts the core distinction between an address computed at compile time (record offset) and one stored as data at run time (pointer), so those options fail.
\[ \boxed{\text{Option B}} \]Consider the following instruction sequence where registers \( R1 \), \( R2 \), and \( R3 \) are general purpose and MEMORY[X] denotes the content at the memory location \( X \):
\[\begin{array}{|l|l|c|} \hline \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size (bytes)} \\ \hline \text{MOV R1, (5000)} & \text{\( R1 \leftarrow \text{MEMORY}[5000] \)} & \text{4} \\ \hline \text{MOV R2, (R3)} & \text{\( R2 \leftarrow \text{MEMORY}[R3] \)} & \text{4} \\ \hline \text{ADD R2, R1} & \text{\( R2 \leftarrow R1 + R2 \)} & \text{2} \\ \hline \text{MOV (R3), R2} & \text{\( \text{MEMORY}[R3] \leftarrow R2 \)} & \text{4} \\ \hline \text{INC R3} & \text{\( R3 \leftarrow R3 + 1 \)} & \text{2} \\ \hline \text{DEC R1} & \text{\( R1 \leftarrow R1 - 1 \)} & \text{2} \\ \hline \text{BNZ 1004} & \text{Branch if not zero to the given absolute address} & \text{2} \\ \hline \text{HALT} & \text{Stop} & \text{1} \\ \hline \end{array}\]Assume that the content of memory location 5000 is 10, and the content of register \( R3 \) is 3000. The content of each of the memory locations from 3000 to 3010 is 50. The instruction sequence starts from memory location 1000. All numbers are in decimal format and the memory is byte addressable.
After the execution of the program, the content of memory location 3010 is \(\underline{\hspace{2cm}}\).