In the circuit shown in the Figure, A and B are logic inputs and Y is the logic output. Which of the following logic operations is realized by the circuit?
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Series PMOS in the pull-up network together with parallel NMOS in the pull-down network is the standard CMOS structure for a NOR gate.
Step 1: Write the pull-up condition in Boolean form. A PMOS conducts on a low gate signal, so the PMOS gated by A conducts when $\overline{A}$ is true, and the one gated by B conducts when $\overline{B}$ is true. Since these two PMOS devices are wired in series, the pull-up path is complete only when both conduct together, so the pull-up condition is the AND of the two: $\overline{A}\cdot\overline{B}$.
Step 2: Connect the pull-up condition to the output. In a fully complementary CMOS gate, $Y$ is high exactly when the pull-up network conducts, so \[ Y=\overline{A}\cdot\overline{B} \]
Step 3: Simplify with De Morgan's theorem. \[ \overline{A}\cdot\overline{B}=\overline{A+B} \] so \[ Y=\overline{A+B} \]
Step 4: Check this against the pull-down network. The pull-down side has an NMOS gated by A and one gated by B wired in parallel, each conducting on a high gate signal. This pulls $Y$ low whenever $A+B$ is true, which is exactly the complementary condition to the pull-up expression above, confirming consistency between the two networks.
Step 5: Name the function. $Y=\overline{A+B}$ is, by definition, the NOR function of $A$ and $B$. \[ \boxed{Y=\overline{A+B}=\text{NOR}(A,B)} \]
