Question

For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is ___________ (rounded off to the nearest integer). 

 

Hint:

In sequential circuits with feedback loops, like latches and flip-flops, the critical path delay is often related to the time it takes for a signal to propagate around the loop. For this cross-coupled structure, the path is through two gates.

Answer 1

Correct Answer: 2

The circuit is a simple SR latch made of two cross-coupled NAND gates. To determine the critical path delay, we need to analyze the longest path through the gates that an input change would propagate to affect the output.

The critical path in this circuit occurs when a change in one input travels through both NAND gates before affecting the final output.
Given:

• Propagation delay per NAND gate: 1 ns

Steps:

1. Analyze the inputs. When a change in input A occurs, it first affects the output of the first NAND gate.
2. This output change then propagates to the second NAND gate.
3. The change in the second NAND gate's output completes the delay path.

The total delay through this path is the sum of the delays of the two NAND gates: 
Critical path delay = 1 ns (first NAND gate) + 1 ns (second NAND gate) = 2 ns.

 

Final Value: The critical path delay is 2 ns. The calculated delay is within the provided range of 2,2.