Consider a processor P whose instruction set architecture is the load-store
architecture. The instruction format is such that the first operand of any instruction
is the destination operand.
Which one of the following sequences of instructions corresponds to the high-level
language statement Z = X + Y ?
Note: X, Y, and Z are memory operands. R0, R1, and R2 are registers.
Instead of checking each option line by line, we can reason from what a load-store machine's ADD instruction is even capable of, and then match that capability to what's needed.
Step 1: What can the ADD instruction touch? By definition of "load-store," an ALU instruction like ADD can only read and write registers - never memory. So any option where ADD lists a memory operand (X, Y, or Z) anywhere in it is automatically wrong, regardless of how many LOADs precede it.
Step 2: Scan the source and destination operands of ADD in each option.
"ADD Z, X, Y" - all three operands are memory. Fails immediately.
"LOAD R0, X" then "ADD Z, R0, Y" - ADD's destination Z and one source Y are still memory. Fails.
"ADD R0, X, Y" then "STORE Z, R0" - ADD's two sources X, Y are memory (only its destination R0 happens to be a register). Fails.
"LOAD R0, X", "LOAD R1, Y", "ADD R2, R0, R1", "STORE Z, R2" - ADD's operands are R2, R0, R1, all registers. Passes.
Step 3: Confirm the data actually flows correctly. X is loaded into R0, Y into R1, their sum computed into R2 by a pure register-to-register ADD, and finally R2 is stored back to memory location Z - exactly reproducing \(Z = X + Y\).
Step 4: Conclude. Only the fourth sequence keeps every ADD operand in registers while still correctly computing and storing the sum, so it is the valid load-store implementation.
Final Answer: option (D).