Question

Consider a 3-stage pipelined processor having a delay of 10 ns, 20 ns, and 14 ns for the first, second, and third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.
The total execution time for executing 100 instructions on this processor is ________ ns.

Hint:

For an ideal $k$-stage pipeline with no hazards and negligible latch overhead: $T=(k+N-1)\times \max\{\text{stage delays}\}$. The first instruction takes $kT_c$; each subsequent one completes every $T_c$.

Answer 1

Correct Answer: 2040