Question

Consider a 3-stage pipelined processor having a delay of 10 ns, 20 ns, and 14 ns for the first, second, and third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.
The total execution time for executing 100 instructions on this processor is ________ ns.

Hint:

For an ideal $k$-stage pipeline with no hazards and negligible latch overhead: $T=(k+N-1)\times \max\{\text{stage delays}\}$. The first instruction takes $kT_c$; each subsequent one completes every $T_c$.

Answer 1

Step 1: Identify instruction issue rate

Once the pipeline is filled, one instruction completes every clock cycle. Hence, the execution speed depends on the slowest stage delay.

Stage delays are:
10 ns, 20 ns, and 14 ns

Pipeline clock period = 20 ns

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Step 2: Account for pipeline filling

A 3-stage pipeline requires 2 extra cycles to fill before steady-state execution begins.

Total cycles needed:

100 (instructions) + 2 (fill cycles) = 102 cycles

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Step 3: Compute total execution time

Each cycle takes 20 ns, so total execution time is:

102 × 20 = 2040 ns

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Final Answer:

2040 ns