A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay. Which of the following options gives the correct binary representation \(b_7b_6b_5b_4b_3b_2b_1b_0\) of the content of the shift register immediately after the \(5^{th}\) clock transition (positive edge)?
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Trace the D flip-flop and XOR feedback state after each clock edge, five times.
Step 1: Note what feeds what.
The XOR gate has a constant $1$ on one leg, so it behaves as a plain inverter on the other leg. That means the bit going into $b_0$ every edge is just the flip-flop output flipped. The flip-flop itself samples whatever bit is currently sitting in $b_7$, the bit that is about to leave the register on that same edge.
Step 2: Build a running table.
Start everything at $0$: register $00000000$ and flip-flop $Q=0$. On every edge, first copy $b_7$ into a "next $Q$" slot, then shift the whole register one place left, and finally drop $\overline{Q}$ (the OLD $Q$, before this edge updates it) into $b_0$.
Step 3: Run five edges.
Edge $1$: old $Q=0$, so $b_0$ gets $\overline{0}=1$. Register becomes $00000001$; new $Q=0$ (old $b_7=0$).
Edge $2$: old $Q=0$, so $b_0$ gets $1$ again. Register becomes $00000011$; new $Q=0$.
Edge $3$: same pattern, register becomes $00000111$; $Q$ stays $0$.
Edge $4$: register becomes $00001111$; $Q$ stays $0$.
Edge $5$: register becomes $00011111$; $Q$ stays $0$.
Step 4: Notice why $Q$ never changes.
Since $b_7$ stays $0$ right through the fifth edge (the block of $1$s takes five edges to even reach position $b_3$, let alone $b_7$), the flip-flop keeps sampling a $0$ and keeps outputting $0$, so the inverter keeps injecting fresh $1$s at $b_0$ every single edge. This is exactly why the pattern grows one $1$ at a time from the right.
Step 5: Read off the answer.
After five edges the register reads $b_7b_6b_5b_4b_3b_2b_1b_0=00011111$.
\[ \boxed{00011111} \]
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