Question

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ______ (rounded off to two decimal places).

Note: \(1\text{G}=10^{9}\)

Hint:

Find execution time per instruction for both designs using time = CPI divided by clock frequency, remembering the pipelined CPI must include the extra stall cycles for 30% of instructions, then take the ratio of the two times.

Answer 1

Correct Answer: 2.3

Step 1: Pick a convenient batch of instructions.
Say the program has $100$ instructions. This makes the percentages easy to turn into instruction counts.

Step 2: Time for the non-pipelined design.
Clock period is $\dfrac{1}{1.6\text{ GHz}} = 0.625$ ns, and each instruction takes $5$ cycles, so one instruction takes $5\times0.625=3.125$ ns. For $100$ instructions the total time is
$100\times3.125 = 312.5$ ns.

Step 3: Time for the pipelined design.
Clock period here is $\dfrac{1}{1.2\text{ GHz}} \approx 0.8333$ ns. Out of the $100$ instructions, $70$ finish in $1$ cycle and $30$ face a stall of $2$ extra cycles, so they take $3$ cycles each. Total cycles needed:
$70\times1 + 30\times3 = 70+90=160$ cycles.
Total time:
$160\times0.8333 \approx 133.33$ ns.

Step 4: Divide the two times.
$\text{Speed-up} = \dfrac{312.5}{133.33} \approx 2.34$
Working with actual instruction counts instead of rates gives the same result as before, which confirms the answer.
\[ \boxed{2.34} \]