Only in the remaining 5% of cases does the access proceed beyond L1. When this happens, the request reaches the L2 cache, where it is satisfied with probability 85% at an effective time of 20 ns. If L2 also fails, which occurs in 15% of L1 misses, the access finally goes to main memory, costing 200 ns.
The average extra delay incurred during an L1 miss is therefore:
\(0.85 \times 20 + 0.15 \times 200 = 47\)
Since this situation arises only 5% of the time, its contribution to the overall access time is:
\(0.05 \times 47 = 2.35\)
Adding this to the typical L1 access time:
\(10 \times 0.95 + 2.35 = 11.85\)
Hence, the average memory access time is \(\boxed{11.85 \text{ ns}}\).
