Question

A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is ___________ . (rounded off to two decimal places)

Hint:

Pipeline execution time depends on the slowest stage plus latch delays.

Answer 1

Correct Answer: 260.2

In a pipelined processor, each instruction advances one stage per clock cycle. The duration of a clock cycle must be long enough to accommodate the slowest processing stage along with the delay introduced by the inter-stage latch.

Among the given stage delays \(180, 250, 150, 170, 250\) ns, the longest delay is \(250\) ns. Including the latch delay of \(10\) ns, each clock cycle lasts \(260\) ns.

The pipeline consists of five stages, so the first instruction completes after five clock cycles. Each subsequent instruction then completes at the rate of one per cycle.

For a total of \(1000\) instructions, the overall execution time is:

\((5 + 999) \times 260 = 261040 \text{ ns}\)

Converting to microseconds:

\(261040 \text{ ns} = 261.04 \,\mu\text{s}\)

Hence, the total execution time lies in the range \(260.20\) to \(261.20\) microseconds.