A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input \( P_0 \) is set to logic ‘0’ and \( P_1 \) is set to logic ‘1’ at all times. The timing diagram of the inputs \( SEL \) and \( S \) are also shown below. The sequence of output \( Y \) from time \( T_0 \) to \( T_3 \) is _________.

The identical MOSFETs \( M_1 \) and \( M_2 \) in the circuit given below are ideal and biased in the saturation region. \( M_1 \) and \( M_2 \) have a transconductance \( g_m \) of 5 mS. The input signals (in Volts) are: \[ V_1 = 2.5 + 0.01 \sin \omega t, \quad V_2 = 2.5 - 0.01 \sin \omega t. \] The output signal \( V_3 \) (in Volts) is _________.
