Consider a 2-bit saturating up/down counter that performs the saturating up count when the input \(P\) is 0, and the saturating down count when \(P\) is 1. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops.
| Input P | Current State Q1 | Current State Q0 | Next State Q1+ | Next State Q0+ |
|---|
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |
Which one of the following options corresponds to the expressions for the inputs of the D flip-flops, \(D_1\) and \(D_0\)?